EP1S25F672C8 Altera, EP1S25F672C8 Datasheet - Page 85

IC STRATIX FPGA 25K LE 672-FBGA

EP1S25F672C8

Manufacturer Part Number
EP1S25F672C8
Description
IC STRATIX FPGA 25K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S25F672C8

Number Of Logic Elements/cells
25660
Number Of Labs/clbs
2566
Total Ram Bits
1944576
Number Of I /o
473
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1119

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Altera Corporation
July 2005
The DSP block is divided into eight block units that interface with eight
LAB rows on the left and right. Each block unit can be considered half of
an 18 × 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local
interconnect region is associated with each DSP block. Like an LAB, this
interconnect region can be fed with 10 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. All row and
column routing resources can access the DSP block’s local interconnect
region. The outputs also work similarly to LAB outputs as well. Nine
outputs from the DSP block can drive to the left LAB through direct link
interconnects and nine can drive to the right LAB though direct link
interconnects. All 18 outputs can drive to all types of row and column
routing. Outputs can drive right- or left-column routing.
and
Figure 2–40. DSP Block Interconnect Interface
2–41
Interconnect
show the DSP block interfaces to LAB rows.
MultiTrack
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
A1[17..0]
DSP Block
OG[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OH[17..0]
OA[17..0]
OF[17..0]
Stratix Device Handbook, Volume 1
Stratix Architecture
MultiTrack
Interconnect
Figures 2–40
2–71

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