EP3C120F780C7N Altera, EP3C120F780C7N Datasheet - Page 70
EP3C120F780C7N
Manufacturer Part Number
EP3C120F780C7N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C7N.pdf
(274 pages)
Specifications of EP3C120F780C7N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2394
544-2532
544-2532
EP3C120F780C7NES
544-2532
544-2532
EP3C120F780C7NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C7N
Manufacturer:
SPANSION
Quantity:
1 000
Company:
Part Number:
EP3C120F780C7N
Manufacturer:
ALTERA
Quantity:
19
2–26
Glossary
Table 2–39. Glossary (Part 1 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
D
G
H
N
O
A
B
C
E
F
K
L
I
J
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
JTAG Waveform
HS CLK
Term
—
—
—
—
—
—
—
—
—
—
Table 2–39
V
Captured
High-speed I/O Block: High-speed receiver and transmitter input and output clock frequency.
Input pin directly to the global clock network.
High-speed I/O Block: Maximum and minimum LVDS data transfer rate (HSIODR = 1/TUI).
Input pin to the global clock network through the PLL.
SWING
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
lists the glossary for this chapter.
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
t
JSH
t
t
JPCO
JSCO
t
t
JPSU_TDI
JPSU_TMS
Definitions
—
—
—
—
—
—
—
—
—
—
t
Chapter 2: Cyclone III LS Device Data Sheet
t
JSXZ
JPH
© December 2009 Altera Corporation
t
JPXZ
V
V
V
REF
IH
IL
Glossary