EP3C120F780C7N Altera, EP3C120F780C7N Datasheet - Page 49
EP3C120F780C7N
Manufacturer Part Number
EP3C120F780C7N
Description
IC CYCLONE III FPGA 119K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C120F780C7N.pdf
(274 pages)
Specifications of EP3C120F780C7N
Number Of Logic Elements/cells
119088
Number Of Labs/clbs
7443
Total Ram Bits
3981312
Number Of I /o
531
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
119088
# I/os (max)
531
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
119088
Ram Bits
3981312
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2394
544-2532
544-2532
EP3C120F780C7NES
544-2532
544-2532
EP3C120F780C7NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C120F780C7N
Manufacturer:
SPANSION
Quantity:
1 000
Company:
Part Number:
EP3C120F780C7N
Manufacturer:
ALTERA
Quantity:
19
Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
Table 2–5. Cyclone III LS Devices Bus Hold Parameters
© December 2009
Bus-hold
low,
sustaining
current
Bus-hold
high,
sustaining
current
Bus-hold
low,
overdrive
current
Bus-hold
high,
overdrive
current
Bus-hold
trip point
Note to
(1) Bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter
Table
2–5:
V
(maximum)
V
(minimum)
0 V < V
0 V < V
IN
IN
Altera Corporation
Condition
> V
< V
IL
IL
—
IN
IN
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 2–5
input pin capacitances and OCT tolerance specifications.
OCT Specifications
Table 2–6
and voltage (PVT).
Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications
< V
< V
Series OCT without
CC IO
CC IO
Description
calibration
Min
0.3
–8
—
—
8
lists the bus hold specifications for Cyclone III LS devices. Also listed are the
lists the variation of OCT without calibration across process, temperature,
1.2
–125
Max
125
0.9
—
—
0.375 1.125 0.68
Min
–12
12
—
—
V
CCIO
3.0
2.5
1.8
1.5
1.2
1.5
(V)
–175
Max
175
(Note 1)
—
—
Min
–30
30
—
—
Commercial Max
1.8
–200
Max
1.07
V
200
—
—
CC IO
±30
±30
±40
±50
±50
(V)
Resistance Tolerance
Min
–50
0.7
50
—
—
2.5
–300
Max
300
1.7
—
—
Cyclone III Device Handbook, Volume 2
Min Max
–70
0.8
70
—
—
3.0
Industrial Max
–500
500
2.0
—
—
±40
±40
±50
±50
±50
Min
–70
0.8
70
—
—
3.3
–500
Max
500
2.0
—
—
Unit
%
%
%
%
%
Unit
μA
μA
μA
μA
V
2–5