EP20K400EBC652-3N Altera, EP20K400EBC652-3N Datasheet - Page 59

IC APEX 20KE FPGA 400K 652-BGA

EP20K400EBC652-3N

Manufacturer Part Number
EP20K400EBC652-3N
Description
IC APEX 20KE FPGA 400K 652-BGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K400EBC652-3N

Number Of Logic Elements/cells
16640
Number Of Labs/clbs
1664
Total Ram Bits
212992
Number Of I /o
488
Number Of Gates
1052000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
652-BGA
Family Name
APEX 20K
Number Of Usable Gates
400000
Number Of Logic Blocks/elements
16640
# I/os (max)
488
Frequency (max)
213MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
16640
Ram Bits
212992
Device System Gates
1052000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
652
Package Type
BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP20K400EBC652-3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP20K400EBC652-3N
Manufacturer:
ALTERA
0
Altera Corporation
Operating
Conditions
Symbol
V
V
V
I
T
T
T
OUT
Table 23. APEX 20K 5.0-V Tolerant Device Absolute Maximum Ratings
STG
AMB
J
CCIO
CCINT
I
Supply voltage
DC input voltage
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
Parameter
Figure 32. APEX 20K AC Test Conditions
Note to
(1)
Tables 23
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V APEX 20K devices.
Device
Output
Power supply transients can affect AC measurements. Simultaneous transitions of
multiple outputs should be avoided for accurate measurement. Threshold tests
must not be performed under AC conditions. Large-amplitude, fast-ground-
current transients normally occur as the device outputs discharge the load
capacitances. When these transients flow through the parasitic inductance between
the device ground pin and the test system ground, significant reductions in
observable noise immunity can result.
Figure
Device input
rise and fall
times < 3 ns
With respect to ground
No bias
Under bias
PQFP, RQFP, TQFP, and BGA packages,
under bias
Ceramic PGA packages, under bias
through
32:
APEX 20K Programmable Logic Device Family Data Sheet
26
provide information on absolute maximum ratings,
C1 (includes
JIG capacitance)
Conditions
(3)
to Test
System
Note (1)
Notes
(1),
Min
–0.5
–0.5
–2.0
–25
–65
–65
(2)
Max
5.75
150
135
135
150
3.6
4.6
25
Unit
mA
° C
° C
° C
° C
V
V
V
59

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