EP1SGX10CF672C7 Altera, EP1SGX10CF672C7 Datasheet - Page 42
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10CF672C7
Manufacturer Part Number
EP1SGX10CF672C7
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10CF672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Figure 2–27. EP1SGX40G Device Inter-Transceiver & Global Clock Connections
Notes to
(1)
(2)
(3)
2–32
Stratix GX Device Handbook, Volume 1
IQ lines are inter-transceiver block lines.
If the /2 pre-divider is used, the path to drive the PLD logic array, local, or global clocks is not allowed.
There are four receiver PLLs in each transceiver block.
Figure
IQ0
2–27:
IQ1
IQ2
refclkb
refclkb
refclkb
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
refclkb
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
Global Clks, I/O Bus, Gen Routing
refclkb
Transceiver Block 0
Transceiver Block 1
Transceiver Block 2
Transceiver Block 3
Transceiver Block 4
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
IQ0
IQ1
IQ2
IQ0
IQ1
/2
/2
IQ2
/2
/2
/2
TX PLL
TX PLL
TX PLL
TX PLL
TX PLL
Receiver
Receiver
Receiver
Receiver
Receiver
PLLs
PLLs
PLLS
PLLs
PLLs
4
4
4
4
4
4
4
4
4
4
(2)
(2)
(2)
Note (1)
Altera Corporation
Clocks
Global
16
PLD
June 2006
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