EP1SGX10CF672C7 Altera, EP1SGX10CF672C7 Datasheet - Page 12
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10CF672C7
Manufacturer Part Number
EP1SGX10CF672C7
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10CF672C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Figure 2–1. Stratix GX Transceiver Block
Notes to
(1)
(2)
2–2
Stratix GX Device Handbook, Volume 1
Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer
to the section
For possible transmitter PLL clock inputs, refer to the section
Logic
Array
Logic
Array
Logic
Array
Logic
Array
Logic
Array
PLD
PLD
PLD
PLD
PLD
Figure
2–1:
“Receiver Path” on page
Receiver
Machine
State
XAUI
Transmitter
Machine
2–13.
State
Transmitter Channel 0
Transmitter Channel 1
XAUI
Transmitter Channel 2
Transmitter Channel 3
Receiver Channel 0
Receiver Channel 1
Receiver Channel 2
Receiver Channel 3
Note (1)
Channel 0
Channel 1
Channel 2
Channel 3
Channel
Machine
Aligner
State
“Transmitter Path” on page
Transmitter
PLL
2–5.
Altera Corporation
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Receiver Pins
Transmitter Pins
Logic
Array
PLD
(2)
June 2006
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