EP1S10F484C6N Altera, EP1S10F484C6N Datasheet - Page 204
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C6N
Manufacturer Part Number
EP1S10F484C6N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Timing Model
4–34
Stratix Device Handbook, Volume 1
Table 4–52
regional clock networks.
Table 4–53
regional clock networks.
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
INSU
INH
OUTCO
XZ
ZX
INSU
INH
OUTCO
INSUPLL
INHPLL
OUTCOPLL
Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 1
of 2)
Symbol
Symbol
Notes
These timing parameters are sample-tested only.
These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Notes
(1),
Table
shows the external I/O timing parameters when using fast
shows the external I/O timing parameters when using
Setup time for input or bidirectional pin using IOE input register with
fast regional clock fed by
Hold time for input or bidirectional pin using IOE input register with
fast regional clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with fast regional clock fed by
Synchronous IOE output enable register to output pin disable delay
using fast regional clock fed by
Synchronous IOE output enable register to output pin enable delay
using fast regional clock fed by
(2)
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by
Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock fed by
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock Enhanced PLL with default phase setting
(1),
4–52:
(2)
CLK
CLK
FCLK
FCLK
pin
pin
Parameter
Parameter
FCLK
pin
pin
FCLK
CLK
FCLK
pin
pin
pin
pin
Altera Corporation
January 2006
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