EP1S10F484C6N Altera, EP1S10F484C6N Datasheet - Page 196
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C6N
Manufacturer Part Number
EP1S10F484C6N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Timing Model
4–26
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
MRAMDATABH
MRAMADDRBSU
MRAMADDRBH
MRAMDATACO1
MRAMDATACO2
MRAMCLKHL
MRAMCLR
Table 4–42. M-RAM Block Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
B port hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in
reported by the timing analyzer in the Quartus II software.
Minimum clear pulse width.
Parameter
Table 4–36 on page 4–20
Altera Corporation
January 2006
and as
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