EP3C80F780C8 Altera, EP3C80F780C8 Datasheet - Page 72
![IC CYCLONE III FPGA 80K 780FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP3C80F780C8
Manufacturer Part Number
EP3C80F780C8
Description
IC CYCLONE III FPGA 80K 780FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
Specifications of EP3C80F780C8
Number Of Logic Elements/cells
81264
Number Of Labs/clbs
5079
Total Ram Bits
2810880
Number Of I /o
429
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
For Use With
544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-2522
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C80F780C8N
Manufacturer:
ALTERA
Quantity:
380
Part Number:
EP3C80F780C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
2–28
Table 2–39. Glossary (Part 3 of 5)
Cyclone III Device Handbook, Volume 2
Letter
S
T
Single-ended
Voltage
referenced I/O
Standard
SW (Sampling
Window)
t
TCCS (Channel-
to-channel-skew)
tcin
t
tcout
t
t
t
Timing Unit
Interval (TUI)
t
t
t
tpllcin
tpllcout
C
C O
DUTY
FA LL
H
INJITTER
OUTJITTER_DEDC LK
OUTJITTER_IO
Term
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values.
■
■
After the receiver input crosses the AC value, the receiver changes to the new logic state. The
new logic state is then maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input waveform
ringing.
High-speed I/O Block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling
window.
High-speed receiver and transmitter input and output clock period.
High-speed I/O Block: The timing difference between the fastest and slowest output edges,
including t
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
High-speed I/O Block: Duty cycle on the high-speed transmitter output clock.
Signal high-to-low transition time (80 to 20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and the data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Delay from the clock pad to the I/O output register.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications.
The DC values indicate the voltage levels at which the final logic state of the receiver is
unambiguously defined.
V
V
OH
OL
C O
variation and clock skew. The clock is included in the TCCS measurement.
V
Definitions
REF
Chapter 2: Cyclone III LS Device Data Sheet
© December 2009 Altera Corporation
V
V
IH(DC)
IL(DC)
V
V
IH ( AC )
IL(AC )
V
CCIO
V
SS
C
/w).
Glossary