EP3C55F484I7 Altera, EP3C55F484I7 Datasheet - Page 40

• Manufacturer Part Number: EP3C55F484I7
• Description: IC CYCLONE III FPGA 55K 484 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C55F484I7

• Number Of Logic Elements/cells: 55856
• Number Of Labs/clbs: 3491
• Total Ram Bits: 2396160
• Number Of I /o: 327
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Page 40
Design and Compilation
Pin-Related Assignments
Selectable I/O capabilities increase the flexibility of Cyclone III devices to connect to
other devices in many low-cost applications. Integration of various I/O-related
features further reduces the cost of any application with Cyclone III devices. Notable
features include current strength control, slew rate control, open-drain, bus hold, PCI
clamp diode, weak pull-up, series on-chip termination, and dedicated output buffer
with programmable pre-emphasis. The following sub-sections discuss the
considerations involved when you use some of the features.
f
For more information about each I/O features, refer to the
Cyclone III Device I/O
Features
chapter in volume 1 of the Cyclone III Device Handbook.
Current Strength and Slew Rate Control
Each I/O standard supports a range of programmable current strength. Select a
suitable current strength setting to meet the performance target for your I/O. Note
that higher current strength increases not just I/O performance, but also noise on the
interface. Ensure that the output buffer current strength is sufficiently high without
causing excessive overshoot or undershoot that violates voltage threshold parameters
for the I/O standard. At the same time, the setting should not be too low to cause
stair-step response, which increases edge rate significantly and results in incorrect
clocking if the pin is used as a clock source.
1
Run simulation with Cyclone III IBIS models to determine if your current strength
setting meets the desired performance and the receiver’s input specification.
Cyclone III devices observe a maximum AC voltage of 4.1 V on all the inputs. To
ensure the device reliability, maximum voltage overshoot seen at the Cyclone III
receiver should not exceed the specification. For more details, refer to
AN 447:
Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
If a large data bus is used in which pins may switch simultaneously, Altera
recommends turning on the slew rate control to reduce simultaneous switching
output (SSO) effects such as crosstalk and ground bounce. Slew rate control is only
available in single-ended I/O standards with 8 mA current strength or higher.
Series On-Chip Termination
Series On-Chip Termination (OCT) in Cyclone III devices can be implemented in two
ways; OCT without calibration, and OCT with calibration. Selection factor is mainly
driven by driver impedance accuracy versus cost of additional external components.
OCT without calibration uses driver output capabilities to match its impedance to the
impedance of the transmission line. For higher impedance matching accuracy,
implement OCT with calibration, which takes into account the voltage and
temperature variation. The calibration process starts at the end of configuration and
completes before user mode operation. While providing better accuracy, you must
Ω
Ω
connect two external resistors of 25
±1% or 50
±1% to a pair of R
and R
pins
UP
DN
for the calibration block. A calibration block is available on each side of the device.
Ω
Ω
Calibration to other impedance values other than the recommended 25
or 50
is
possible, which is limited only by range of buffer impedance.
© November 2008 Altera Corporation