EPF10K30RI240-4 Altera, EPF10K30RI240-4 Datasheet - Page 62
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EPF10K30RI240-4
Manufacturer Part Number
EPF10K30RI240-4
Description
IC FLEX 10K FPGA 30K 240-RQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K30RI240-4
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
12288
Number Of I /o
189
Number Of Gates
69000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
240-RQFP
Family Name
FLEX 10K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# Registers
738
# I/os (max)
189
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1728
Ram Bits
12288
Device System Gates
69000
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
RQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-2234
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K30RI240-4
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EPF10K30RI240-4N
Manufacturer:
ALTEAR
Quantity:
500
62
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 35. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Notes
Parameter
(1),
(6)
Altera Corporation
Conditions