EPF10K20RC208-3N Altera, EPF10K20RC208-3N Datasheet - Page 60
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EPF10K20RC208-3N
Manufacturer Part Number
EPF10K20RC208-3N
Description
IC FLEX 10K FPGA 20K 208-RQFP
Manufacturer
Altera
Series
FLEX-10K®r
Datasheet
1.EPF10K10ATC100-3.pdf
(128 pages)
Specifications of EPF10K20RC208-3N
Number Of Logic Elements/cells
1152
Number Of Labs/clbs
144
Total Ram Bits
12288
Number Of I /o
147
Number Of Gates
63000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-RQFP
Family Name
FLEX 10K
Number Of Usable Gates
20000
Number Of Logic Blocks/elements
1152
# I/os (max)
147
Frequency (max)
125MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
5V
Logic Cells
1152
Ram Bits
12288
Device System Gates
63000
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
RQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2208
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF10K20RC208-3N
Manufacturer:
ALTERA
Quantity:
5 530
Company:
Part Number:
EPF10K20RC208-3N
Manufacturer:
ALTERA
Quantity:
6 100
60
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
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t
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t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
PRE
CLR
CH
CL
IOD
IOC
IOCO
IOCOMB
IOSU
IOH
IOCLR
OD1
OD2
OD3
XZ
ZX1
ZX2
ZX3
INREG
IOFD
INCOMB
Table 32. LE Timing Microparameters (Part 2 of 2)
Table 33. IOE Timing Microparameters
Symbol
Symbol
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
LE register hold time for data and enable signals after clock
LE register preset delay
LE register clear delay
Minimum clock high time from clock pin
Minimum clock low time from clock pin
IOE data delay
IOE register control signal delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time for data and enable signals before clock; IOE register
recovery time after asynchronous clear
IOE register hold time for data and enable signals after clock
IOE register clear time
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = off, V
Output buffer and pad delay, slow slew rate = on
IOE output buffer disable delay
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = off, V
IOE output buffer enable delay, slow slew rate = on
IOE input pad and buffer to IOE register delay
IOE register feedback delay
IOE input pad and buffer to FastTrack Interconnect delay
Note (1)
Parameter
Parameter
Note (1)
CCIO
CCIO
CCIO
CCIO
= V
= low voltage
= V
= low voltage
CCINT
CCINT
Altera Corporation
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
Conditions
(2)
(3)
(4)
(2)
(3)
(4)