EP3C25F256C7N Altera, EP3C25F256C7N Datasheet - Page 59

• Manufacturer Part Number: EP3C25F256C7N
• Description: IC CYCLONE III FPGA 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F256C7N

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 156
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 156
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: Q4433068

Chapter 4: Embedded Multipliers in the Cyclone III Device Family
Architecture
Table 4–2. Number of Multipliers in the Cyclone III Device Family (Part 2 of 2)
Architecture
© December 2009
Notes to
(1) Soft multipliers are implemented in sum of multiplication mode. M9K memory blocks are configured with 18-bit data widths to support 16-bit
(2) The total number of multipliers may vary, depending on the multiplier mode you use.
Device Family
Cyclone III LS
coefficients. The sum of the coefficients requires 18-bits of resolution to account for overflow.
Table
f
f
4–2:
Altera Corporation
For more information about M9K memory blocks of the Cyclone III device family,
refer to the
For more information about soft multipliers, refer to
in FPGA Devices.
Each embedded multiplier consists of the following elements:
■
■
■
Figure 4–2
Figure 4–2. Multiplier Block Architecture
EP3CLS100
EP3CLS150
EP3CLS200
EP3CLS70
Multiplier stage
Input and output registers
Input and output interfaces
Device
shows the multiplier block architecture.
Memory Blocks in Cyclone III Devices
Data A
Data B
Embedded Multipliers
D
ENA
D
ENA
CLRN
CLRN
200
276
320
396
signa
signb
clock
Q
Q
ena
aclr
Register
Input
Embedded Multiplier Block
Soft Multipliers
(16
chapter.
D
ENA
× 16)
CLRN
333
483
666
891
Register
Output
AN 306: Implementing Multipliers
Q
(1)
Cyclone III Device Handbook, Volume 1
Total Multipliers
Data Out
1287
533
759
986
(2)
4–3