EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 73
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
Quantity:
2 350
Company:
Part Number:
EP3C25F324C8N
Manufacturer:
ALTERA
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160
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Part Number:
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612
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Manufacturer:
ALTERA/阿尔特拉
Quantity:
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Part Number:
EP3C25F324C8NES
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLLs in the Cyclone III Device Family
PLLs in the Cyclone III Device Family
© December 2009
f
Altera Corporation
Altera recommends using the clkena signals when switching the clock source to the
PLLs or the GCLK. The recommended sequence is:
1. Disable the primary output clock by deasserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control
3. Allow some clock cycles of the secondary clock to pass before reasserting the
The Cyclone III device family offers up to four PLLs that provide robust clock
management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
For more information about the number of PLLs in each device density, refer to the
Cyclone III Device Family Overview
The Cyclone III device family PLLs have the same core analog structure.
Table 5–3
Table 5–3. Cyclone III Device Family PLL Hardware Features
C (output counters)
M, N, C counter sizes
Dedicated clock outputs
Clock input pins
Spread-spectrum input clock tracking
PLL cascading
Compensation modes
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
User mode reconfiguration
Loss of lock detection
Notes to
(1) C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a
(2) Only applicable if the input clock jitter is in the input jitter tolerance specifications.
(3) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
block.
clkena signal. The exact number of clock cycles you must wait before enabling
the secondary clock is design-dependent. You can build custom logic to ensure
glitch-free transition when switching between different clock sources.
non-50% duty cycle, the post-scale counters range from 1 through 256.
degree increments, the Cyclone III device family can shift all output frequencies in increments of at least 45°.
Smaller degree increments are possible depending on the frequency and divide parameters.
Table
lists the features available in the Cyclone III device family PLLs.
5–3:
Hardware Features
chapter.
5
1 to 512
1 single-ended or 1 differential pair
4 single-ended or 2 differential pairs
Through GCLK
Source-Synchronous Mode, No Compensation
Mode, Normal Mode, and Zero Delay Buffer Mode
Down to 96-ps increments
(1)
Cyclone III Device Handbook, Volume 1
Availability
v
v
v
v
v
v
(2)
(3)
5–9