EP3C25F324C8N Altera, EP3C25F324C8N Datasheet - Page 106
![IC CYCLONE III FPGA 25K 324-FBGA](/photos/6/70/67067/544-324-fbga_sml.jpg)
EP3C25F324C8N
Manufacturer Part Number
EP3C25F324C8N
Description
IC CYCLONE III FPGA 25K 324-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C25F324C8N.pdf
(274 pages)
Specifications of EP3C25F324C8N
Number Of Logic Elements/cells
24624
Number Of Labs/clbs
1539
Total Ram Bits
608256
Number Of I /o
215
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
24624
# I/os (max)
215
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
24624
Ram Bits
608256
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2078
EP3C25F324C8NES
EP3C25F324C8NES
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Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
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Quantity:
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6–6
PCI-Clamp Diode
Cyclone III Device Handbook, Volume 1
f
f
f
The IOE registers in each I/O block share the same source for the preset or clear
features. You can program preset or clear for each individual IOE, but you cannot use
both features simultaneously. You can also program the registers to power-up high or
low after configuration is complete. If programmed to power-up low, an
asynchronous clear can control the registers. If programmed to power-up high, an
asynchronous preset can control the registers. This feature prevents the inadvertent
activation of the active-low input of another device upon power up. If one register in
an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if
they require preset or clear. Additionally, a synchronous reset signal is available for
the IOE registers.
For more information about the input and output pin delay settings, refer to the
and Timing Optimization
The Cyclone III device family provides an optional PCI-clamp diode enabled input
and output for each I/O pin. Dual-purpose configuration pins support the diode in
user mode if the specific pins are not used as configuration pins for the selected
configuration scheme. For example, if you are using the active serial (AS)
configuration scheme, you cannot use the clamp diode on the ASDO and nCSO pins in
user mode. Dedicated configuration pins do not support the on-chip diode.
The PCI-clamp diode is available for the following I/O standards:
■
■
■
■
■
■
■
If the input I/O standard is 3.3-V LVTTL, 3.3-V LVCMOS, 3.0-V LVTTL, 3.0-V
LVCMOS, 2.5-V LVTTL/LVCMOS, PCI, or PCI-X, the PCI clamp diode is enabled by
default in the Quartus II software.
For more information, refer to the
Quartus II Handbook.
For more information about the Cyclone III device family PCI-clamp diode support,
refer to
Systems.
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
PCI
PCI-X
AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O
chapter in volume 2 of the Quartus II Handbook.
Assignment Editor
Chapter 6: I/O Features in the Cyclone III Device Family
chapter in volume 2 of the
© December 2009 Altera Corporation
I/O Element Features
Area