EP3C10U256C6N Altera, EP3C10U256C6N Datasheet - Page 27
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EP3C10U256C6N
Manufacturer Part Number
EP3C10U256C6N
Description
IC CYCLONE III FPGA 10K 256-UBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10U256C6N.pdf
(274 pages)
Specifications of EP3C10U256C6N
Number Of Logic Elements/cells
10320
Number Of Labs/clbs
645
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-UBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
10320
# I/os (max)
182
Frequency (max)
500MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
10320
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
UFBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2433
EP3C10U256C6N
EP3C10U256C6N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: Cyclone III Device Data Sheet
I/O Timing
I/O Timing
Glossary
Table 1–39. Glossary (Part 1 of 5)
© January 2010 Altera Corporation
Letter
D
G
H
A
B
C
E
F
I
f
GCLK
GCLK PLL
HSIODR
Input Waveforms
for the SSTL
Differential I/O
Standard
HS CLK
f
Term
—
—
—
—
—
You can use the following methods to determine the I/O timing:
■
■
The Excel-based I/O Timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
The Excel-based I/O Timing spreadsheet is downloadable from
Literature
Table 1–39
the Excel-based I/O Timing.
the Quartus II timing analyzer.
V
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
Input pin directly to Global Clock network.
Input pin to Global Clock network through PLL.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
SWING
website.
lists the glossary for this chapter.
Definitions
—
—
—
—
—
Cyclone III Device Handbook, Volume 2
Cyclone III Devices
V
V
V
REF
IH
IL
1–27