EP1C6F256I7 Altera, EP1C6F256I7 Datasheet - Page 5
![IC CYCLONE FPGA 5980 LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP1C6F256I7
Manufacturer Part Number
EP1C6F256I7
Description
IC CYCLONE FPGA 5980 LE 256-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6F256I7
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
185
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1021
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1C6F256I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C6F256I7N
Manufacturer:
ALTERA41
Quantity:
139
Part Number:
EP1C6F256I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Document
Revision History
Altera Corporation
May 2008
Pitch (mm)
Area (mm
Length × width
(mm × mm)
May 2008
v1.5
January 2007
v1.4
August 2005
v1.3
October 2003
v1.2
September
2003 v1.1
May 2003 v1.0
Table 1–3. Cyclone QFP and FineLine BGA Package Sizes
Table 1–4. Document Revision History
Document
Date and
Dimension
Version
2
)
Added document to Cyclone Device Handbook.
Minor textual and style changes.
Added document revision history.
Minor updates.
Added 64-bit PCI support information.
●
●
Updated LVDS data rates to 640 Mbps from 311 Mbps.
Updated RSDS feature information.
100-Pin
16×16
TQFP
256
0.5
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
Table 1–4
144-Pin
22×22
TQFP
484
shows the revision history for this document.
0.5
Changes Made
34.6×34.6
240-Pin
PQFP
1,024
0.5
FineLine
256-Pin
17×17
BGA
289
1.0
Document Revision History
FineLine
324-Pin
19×19
Summary of Changes
BGA
361
1.0
—
—
—
—
—
—
Preliminary
FineLine
400-Pin
21×21
BGA
441
1.0
1–3