EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 49
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 2: Cyclone III LS Device Data Sheet
Electrical Characteristics
Table 2–5. Cyclone III LS Devices Bus Hold Parameters
© December 2009
Bus-hold
low,
sustaining
current
Bus-hold
high,
sustaining
current
Bus-hold
low,
overdrive
current
Bus-hold
high,
overdrive
current
Bus-hold
trip point
Note to
(1) Bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter
Table
2–5:
V
(maximum)
V
(minimum)
0 V < V
0 V < V
IN
IN
Altera Corporation
Condition
> V
< V
IL
IL
—
IN
IN
Bus Hold
Bus hold retains the last valid logic state after the source driving it either enters the
high impedance state or is removed. Each I/O pin has an option to enable bus hold in
user mode. Bus hold is always disabled in configuration mode.
Table 2–5
input pin capacitances and OCT tolerance specifications.
OCT Specifications
Table 2–6
and voltage (PVT).
Table 2–6. Cyclone III LS Devices Series OCT without Calibration Specifications
< V
< V
Series OCT without
CC IO
CC IO
Description
calibration
Min
0.3
–8
—
—
8
lists the bus hold specifications for Cyclone III LS devices. Also listed are the
lists the variation of OCT without calibration across process, temperature,
1.2
–125
Max
125
0.9
—
—
0.375 1.125 0.68
Min
–12
12
—
—
V
CCIO
3.0
2.5
1.8
1.5
1.2
1.5
(V)
–175
Max
175
(Note 1)
—
—
Min
–30
30
—
—
Commercial Max
1.8
–200
Max
1.07
V
200
—
—
CC IO
±30
±30
±40
±50
±50
(V)
Resistance Tolerance
Min
–50
0.7
50
—
—
2.5
–300
Max
300
1.7
—
—
Cyclone III Device Handbook, Volume 2
Min Max
–70
0.8
70
—
—
3.0
Industrial Max
–500
500
2.0
—
—
±40
±40
±50
±50
±50
Min
–70
0.8
70
—
—
3.3
–500
Max
500
2.0
—
—
Unit
%
%
%
%
%
Unit
μA
μA
μA
μA
V
2–5