EP3C16F484C8N Altera, EP3C16F484C8N Datasheet - Page 38
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C8N
Manufacturer Part Number
EP3C16F484C8N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C8N.pdf
(274 pages)
Specifications of EP3C16F484C8N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
402MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2474
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA
Quantity:
331
Company:
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA44
Quantity:
120
Part Number:
EP3C16F484C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
1–28
Table 1–39. Glossary (Part 2 of 5)
Cyclone III Device Handbook, Volume 2
Letter
M
N
O
Q
K
L
P
J
JTAG Waveform
PLL Block
Term
—
—
—
—
—
—
Captured
The following block diagram highlights the PLL Specification parameters.
Core Clock
Driven
Signal
Signal
to be
to be
Key
TMS
CLK
TDO
TCK
TDI
Reconfigurable in User Mode
t
JCH
t
t
JSZX
JPZX
t
JCP
t
JSSU
t
JCL
Switchover
f
IN
t
JSH
N
t
t
JPCO
JSCO
t
t
f
INPFD
JPSU_TDI
JPSU_TMS
Definitions
PFD
—
—
—
—
—
—
M
CP
t
JSXZ
t
JPH
Phase tap
LF
Chapter 1: Cyclone III Device Data Sheet
VCO
© January 2010 Altera Corporation
t
JPXZ
f
VCO
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
Glossary
GCLK