EP3C16F256C8N Altera, EP3C16F256C8N Datasheet - Page 109

• Manufacturer Part Number: EP3C16F256C8N
• Description: IC CYCLONE III FPGA 16K 256FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F256C8N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 168
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 168
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2464

Chapter 6: I/O Features in the Cyclone III Device Family
OCT Support
© December 2009
Altera Corporation
Figure 6–3
Figure 6–3. Cyclone III Device Family OCT Block Placement
Each calibration block comes with a pair of RUP and RDN pins. When used for
calibration, the RUP pin is connected to V
50-Ω ±1% resistor for an on-chip series termination value of 25 Ω or 50 Ω,
respectively. The RDN pin is connected to GND through an external 25-Ω ±1% or 50-Ω
The external resistors are compared with the internal resistance using comparators.
The resultant outputs of the comparators are used by the OCT calibration block to
dynamically adjust buffer impedance.
During calibration, the resistance of the RUP and RDN pins varies. For an estimate of
the maximum possible current through the external calibration resistors, assume a
minimum resistance of 0 Ω on the RUP and RDN pins during calibration.
±1% resistor for an on-chip series termination value of 25 Ω or 50 Ω, respectively.
shows the top-level view of the OCT calibration blocks placement.
I/O Bank 3
I/O Bank 8
Cyclone III Device Family
I/O Bank 4
I/O Bank 7
CCIO
through an external 25-Ω ±1% or
Cyclone III Device Handbook, Volume 1
I/O bank with
calibration block
I/O bank without
calibration block
Calibration block
coverage
6–9