EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 44
![IC CYCLONE III FPGA 5K 144 EQFP](/photos/6/73/67369/ep3c5e144i7n_sml.jpg)
EP3C5E144I7N
Manufacturer Part Number
EP3C5E144I7N
Description
IC CYCLONE III FPGA 5K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5E144I7N.pdf
(274 pages)
Specifications of EP3C5E144I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2557
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
Altera
Quantity:
135
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA32
Quantity:
345
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 44
Validating Pin Placement
f
f
f
■
■
■
The .pof and .jic files are used with the Quartus II Programmer to program the
configuration devices while the .hexout, .rbf, .ttf, and .rpd files are used with other
programmers.
When working with multi-device configuration chains, you should combine each
device’s .sof file into one configuration file in the Convert Programming Files dialog
box. When generating the configuration file, ensure that the configuration files are in
the same order as the devices on the board.
For more information about setting device configuration options or creating
configuration files, refer to the
Configuration Handbook.
For more information about programming file formats and using the programmer,
refer to the
After creating pin-related assignments, you must validate the assignments against
rules specific to the Cyclone III device. This section discusses the validation and
considerations about pin placement.
I/O Assignment Analysis
The Start I/O Assignment Analysis command allows you to check the legality of
your I/O assignments before, during, or after you compile your design. If design files
are available, you can use this command to perform thorough legality checks on your
design’s I/O pins and surrounding logic. These checks include proper reference
voltage pin usage, valid pin location assignments, and acceptable mixed I/O
standards. Run the analysis each time you add or modify a pin-related assignment.
For more information about the Start I/O Assignment Analysis command and its
design flow, refer to the
Handbook.
DC Guidelines
Sourcing or sinking large amounts of steady current from output pins can damage the
device due to electromigration, where the movement of the conducting metal's atoms
is caused by the large amount of electric current flowing through it. Some examples
pull a high output pin to ground or connect a low output pin to V
maximum DC current a Cyclone III I/O pin can sink is 25 mA and source is 40 mA. If
certain pins have to be pulled high or low, pull them through external resistors.
Tabular Text File (.ttf),
Raw Programming Data (.rpd) file, and
JTAG Indirect Configuration File (.jic).
Quartus II Programmer
I/O Management
Software Settings
chapter in volume 3 of the Quartus II Handbook.
chapter in volume 2 of the Quartus II
section in volume 2 of the
© November 2008 Altera Corporation
CC
Design and Compilation
directly. The