EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 26
![IC CYCLONE III FPGA 5K 144 EQFP](/photos/6/73/67369/ep3c5e144i7n_sml.jpg)
EP3C5E144I7N
Manufacturer Part Number
EP3C5E144I7N
Description
IC CYCLONE III FPGA 5K 144 EQFP
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C5E144I7N.pdf
(274 pages)
Specifications of EP3C5E144I7N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
94
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-EQFP
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
94
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
EQFP
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2557
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
Altera
Quantity:
135
Company:
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA32
Quantity:
345
Part Number:
EP3C5E144I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Page 26
Board Design Considerations
MSEL Configuration Mode Pins
Select the configuration scheme by driving the Cyclone III device MSEL pins either
high or low. The MSEL pins are powered by the V
power supply of the bank in
CCINT
Ω
which they reside. The MSEL[3..0] pins have 5-k
internal pull-down resistors that
are always active. During power-on reset (POR) and during reconfiguration, the MSEL
pins have to be at least LVTTL V
or V
levels to be considered a logic low or logic
IL
IH
high, respectively. To avoid any problems with detecting an incorrect configuration
scheme, hardwire the MSEL pins to V
and GND without any pull-up or pull-down
CCA
resistors. Alternatively, set up your board so that you can connect each pin to either
Ω
V
or GND with a 0-
resistor to change between configuration modes during
CCA
testing or debugging. Altera recommends not to drive the MSEL pins with a
microprocessor or another device.
1
Do not leave the MSEL pins floating.
f
For more information about configuration, refer to the
Configuring Cyclone III Devices
chapter in volume 1 of the Cyclone III Device Handbook. Also refer to the
Configuration
Center, which includes links to troubleshooters that you can use to help debug
configuration problems. To help you debug JTAG programming issues, refer to the
JTAG Configuration & ISP
Troubleshooter. To debug FPGA configuration issues, refer
to the
FPGA Configuration
Troubleshooter.
© November 2008 Altera Corporation