EP3C5E144I7N Altera, EP3C5E144I7N Datasheet - Page 13

• Manufacturer Part Number: EP3C5E144I7N
• Description: IC CYCLONE III FPGA 5K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5E144I7N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 5136
• # I/os (max): 94
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 5136
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2557

Chapter 1: Cyclone III Device Data Sheet
Electrical Characteristics
Table 1–16. Cyclone III Devices Differential SSTL I/O Standard Specifications
Table 1–17. Cyclone III Devices Differential HSTL I/O Standard Specifications
Table 1–18. Cyclone III Devices Differential I/O Standard Specifications
© January 2010 Altera Corporation
SSTL-2
Class I, II
SSTL-18
Class I, II
HSTL-18
Class I, II
HSTL-15
Class I, II
HSTL-12
Class I, II
LVPECL
(Row I/Os)
(4)
LVPECL
(Column
I/Os)
LVDS (Row
I/Os)
LVDS
(Column
I/Os)
BLVDS
(Row I/Os)
(5)
BLVDS
(Column
I/Os)
I/O Standard
I/O Standard
Standard
I/O
(4)
(5)
2.375
2.375
2.375
2.375
2.375
2.375
2.375
Min
1.425
Min
1.71
1.14
Min
1.7
V
V
V
C CIO
C CIO
Typ
2.5
2.5
2.5
2.5
2.5
2.5
CC IO
Typ
2.5
1.8
Typ
1.8
1.5
1.2
(V)
(V)
(V)
2.625 100
2.625 100
2.625 100
2.625 100
2.625 100
2.625 100
2.625 0.36
1.575
Max
1.90
Max
Max
1.89
1.26
0.25
0.16
Min
Min
Min
V
0.2
0.2
V
V
Swing(D C)
DIF(DC)
ID
(mV)
Max
V
V
Max
—
—
Max
(V)
V
(V)
—
—
—
—
—
—
CC IO
CC IO
C CIO
0.05 D
0.55
1.05 D
0.05 D
0.55
1.05 D
0.05 D
0.55
1.05 D
0.05 D
0.55
1.05 D
Min
V
0.48 * V
—
—
CC IO
V
0.175
CC IO
0.85
0.71
Min
/2 – 0.2
Min
/2 –
500 Mbps ≤ D
700 Mbps
500 Mbps ≤ D
700 Mbps
500 Mbps ≤ D
500 Mbps ≤ D
700 Mbps
700 Mbps
M AX
M AX
M AX
M AX
M AX
M AX
M AX
M AX
CC IO
V
V
> 700 Mbps
> 700 Mbps
Condition
> 700 Mbps
> 700 Mbps
≤ 500 Mbps
≤ 500 Mbps
≤ 500 Mbps
≤ 500 Mbps
V
IcM
X (A C)
X(A C)
Typ
(V)
—
—
Typ
—
—
—
—
—
(V)
(V)
(2)
(Note 1)
M AX
M AX
M AX
M AX
V
V
0.52 *
0.175
C CIO
C CIO
≤
≤
≤
Max
Max
0.95
0.79
≤
V
0.2
CC IO
/2 +
/2 +
Max Min Typ
1.80
1.80
1.55
1.80
1.80
1.55
1.80
1.80
1.55
1.80
1.80
1.55
—
—
(Part 1 of 2)
Min Max
V
0.7
0.5
Sw ing(AC )
0.48 *
247
247
0.85
0.71
Min
—
—
—
—
V
C CIO
V
Cyclone III Device Handbook, Volume 2
V
V
O D
(V)
CC IO
CC IO
(mV)
—
—
—
—
—
—
V
CM (D C)
Typ
—
—
—
(3)
V
V
Max
600
600
0.125
0.125
(V)
—
—
—
—
C CIO
C CIO
Min
/2 –
/2 –
0.52 *
Max
0.95
0.79
V
1.125 1.25 1.375
1.125 1.25 1.375
Min
V
CCIO
—
—
—
—
OX (AC)
Typ
V
—
—
(V)
O S
Typ
(V)
—
—
—
—
0.4
0.4
0.3
Mi
n
V
V
V
(3)
D IF(A C)
1–13
0.125
0.125
CC IO
CC IO
Max
0.48 *
Max
/2 +
/2 +
Max
V
—
—
—
—
(V)
—
—
CCIO