EP3C5M164C7N Altera, EP3C5M164C7N Datasheet - Page 40

IC CYCLONE III FPGA 5K 164 MBGA

EP3C5M164C7N

Manufacturer Part Number
EP3C5M164C7N
Description
IC CYCLONE III FPGA 5K 164 MBGA
Manufacturer
Altera
Series
Cyclone® IIIr

Specifications of EP3C5M164C7N

Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
106
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
164-MBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
5136
# I/os (max)
106
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
5136
Ram Bits
423936
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
164
Package Type
MBGA
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2559

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
ALTERA
Quantity:
526
Part Number:
EP3C5M164C7N
Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
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0
1–30
Table 1–39. Glossary (Part 4 of 5)
Cyclone III Device Handbook, Volume 2
Letter
U
T
t
TCCS (Channel-
to-channel-skew)
tcin
t
tcout
t
t
t
Timing Unit
Interval (TUI)
t
t
t
tpllcin
tpllcout
Transmitter
Output Waveform
t
t
C
C O
DUTY
FA LL
H
INJITTER
OUTJITTER_DEDC LK
OUTJITTER_IO
RISE
S U
Term
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards
Signal Low-to-high transition time (20–80%).
Input register setup time.
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
C O
variation and clock skew. The clock is included in the TCCS measurement.
V os
V
OD
V
OD
Definitions
Chapter 1: Cyclone III Device Data Sheet
V
OD
© January 2010 Altera Corporation
Positive Channel (p) = V
Negative Channel (n) = V
Ground
0 V
p - n
C
/w).
OH
OL
Glossary

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