XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 88
![IC SPARTAN-3E FPGA 250K 256-FTBG](/photos/6/71/67101/pk053-256_sml.jpg)
XC3S250E-4FTG256C
Manufacturer Part Number
XC3S250E-4FTG256C
Description
IC SPARTAN-3E FPGA 250K 256-FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4FTG256C
Total Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Number Of I /o
172
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
5508
No. Of Gates
250000
No. Of Macrocells
5508
No. Of Speed Grades
4
No. Of I/o's
190
Clock Management
DLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1482
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Quantity
Price
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Functional Description
Table 59: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
88
LDC1
HDC
LDC2
A[23:0]
D[7:0]
CSO_B
BUSY
D
Pin Name
FPGA Direction
Output
Output
Output
Output
Output
Output
Input
PROM Output Enable
PROM Write Enable
PROM Byte Mode
Address
Data Input
Chip Select Output. Active Low.
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Description
www.xilinx.com
Connect to the PROM
output-enable input (OE#). The
FPGA drives this signal Low
throughout configuration.
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
This signal is not used for x8
PROMs. For PROMs with a x8/x16
data width control, connect to
PROM byte-mode input (BYTE#).
See
Flash
signal Low throughout
configuration.
Connect to PROM address inputs.
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends
on the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA on rising
edge of CCLK.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to
a 4.7 kΩ pull-up resistor to
VCCO_2. Actively drives Low
when selecting a downstream
device in the chain.
Not used during configuration but
actively drives.
Precautions Using x8/x16
During Configuration
PROMs. FPGA drives this
DS312-2 (v3.8) August 26, 2009
User I/O
User I/O
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in x16
mode.
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
After Configuration
Product Specification
R