XC3S250E-4FTG256C Xilinx Inc, XC3S250E-4FTG256C Datasheet - Page 36
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XC3S250E-4FTG256C
Manufacturer Part Number
XC3S250E-4FTG256C
Description
IC SPARTAN-3E FPGA 250K 256-FTBG
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4FTG256C
Total Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Number Of I /o
172
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-LBGA
No. Of Logic Blocks
5508
No. Of Gates
250000
No. Of Macrocells
5508
No. Of Speed Grades
4
No. Of I/o's
190
Clock Management
DLL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1482
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S250E-4FTG256C
Manufacturer:
TOS
Quantity:
3 012
Company:
Part Number:
XC3S250E-4FTG256C
Manufacturer:
XILINX
Quantity:
281
Part Number:
XC3S250E-4FTG256C
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Functional Description
Table 22: Port Aspect Ratios
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words. Par-
36
Notes:
1.
2.
3.
4.
Path Width
Total Data
(w bits)
The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log(2)].
The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2
The product of w and n yields the total block RAM capacity.
18
36
1
2
4
9
DI/DO Data
Bus Width
(w-p bits)
Figure
16
32
1
2
4
8
31. When data is written to a port
1
Parity Bus
DIP/DOP
(p bits)
Width
0
0
0
1
2
4
(r bits)
ADDR
Width
Bus
14
13
12
11
10
9
2
www.xilinx.com
[w-p-1:0]
DI/DO
[15:0]
[31:0]
[0:0]
[1:0]
[3:0]
[7:0]
ity bits are not available if the data port width is configured
as x4, x2, or x1. For example, if a x36 data word (32 data, 4
parity) is addressed as two x18 halfwords (16 data, 2 par-
ity), the parity bits associated with each data byte are
mapped within the block RAM to the appropriate parity bits.
The same effect happens when the x36 data word is
mapped as four x9 words.
DIP/DOP
[p-1:0]
[0:0]
[1:0]
[3:0]
-
-
-
ADDR
[r-1:0]
[13:0]
[12:0]
[11:0]
[10:0]
[9:0]
[8:0]
Locations (n)
Addressable
DS312-2 (v3.8) August 26, 2009
16,384
No. of
8,192
4,096
2,048
1,024
512
Product Specification
3
Block RAM
(w*n bits)
Capacity
16,384
16,384
16,384
18,432
18,432
18,432
r
.
4
R