EP2S60F672C4N Altera, EP2S60F672C4N Datasheet - Page 82

• Manufacturer Part Number: EP2S60F672C4N
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672C4N

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1913; EP2S60F672C4N

I/O Structure
Figure 2–49. Signal Path through the I/O Block
2–74
Stratix II Device Handbook, Volume 1
From Logic
To Logic
Array
Array
Row or Column
io_dataouta
io_dataoutb
io_clk[7..0]
io_dataina
io_datainb
io_ce_out
io_ce_in
io_aclr
io_sclr
io_clk
io_oe
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (see the
Figure 2–49
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out.
selection.
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
Figure 2–50
To Other
IOEs
“PLLs & Clock Networks”
illustrates the control signal
IOE
Altera Corporation
section).
May 2007