EP1S20F484I6 Altera, EP1S20F484I6 Datasheet - Page 189

• Manufacturer Part Number: EP1S20F484I6
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484I6

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 361
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2086

Timing Model
Altera Corporation
January 2006
The DirectDrive
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix device densities and speed grades. This section
describes and specifies the performance, internal, external, and PLL
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Stratix device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Table 4–35. Stratix Device Timing Model Status
EP1S10
EP1S20
EP1S25
EP1S30
EP1S40
EP1S60
EP1S80
Device
™
technology and MultiTrack
Preliminary
Table 4–35
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
™
interconnect ensure
shows the status of the
Final
v
v
v
v
v
v
v
4–19