EP2SGX30DF780I4N Altera, EP2SGX30DF780I4N Datasheet - Page 125

• Manufacturer Part Number: EP2SGX30DF780I4N
• Description: IC STRATIX II GX 30K 780-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX30DF780I4N

• Number Of Logic Elements/cells: 33880
• Number Of Labs/clbs: 1694
• Total Ram Bits: 1369728
• Number Of I /o: 361
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2177

Figure 2–81. Stratix II GX IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–81:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
The Stratix II GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Output Register
Input Register
OE Register
D
CLRN/PRN
ENA
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Output
Input Register Delay
Logic Array Delay
Stratix II GX Device Handbook, Volume 1
Input Pin to
Input Pin to
Note (1)
OE Register
t
CO
Delay
V
Stratix II GX Architecture
CCIO
PCI Clamp (2)
V
CCIO
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–117