EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 208
EP2SGX30CF780C4N
Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N
EP2SGX30CF780C4N
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Manufacturer
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Operating Conditions
4–38
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Serial RapidIO
SDI
BASIC Single
Width
BASIC Double
Width
Table 4–21. PCS Latency (Part 2 of 2)
Functional Mode
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the
chapter in volume 2 of the Stratix II GX Device Handbook.
Table
4–21:
10-bit channel
20-bit channel
Configuration
channel width
channel width
channel width
channel width
16-bit/20-bit
16-bit/20-bit
32-bit/40-bit
3.125 Gbps
1.25 Gbps,
8-bit/10-bit
Loopback/
2.5 Gbps,
HD, 3G
Parallel
width
width
BIST
HD
TX PIPE
Note (1)
-
-
-
-
-
-
-
-
Phase
Comp
FIFO
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
TX
Transmitter PCS Latency
Serializer
Byte
Stratix II GX Transceiver Architecture Overview
1
1
1
1
1
1
1
1
TX State
Machine
-
-
-
-
-
-
-
-
Encoder
8B/10B
0.5
0.5
0.5
0.5
1
1
1
1
Altera Corporation
Sum
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
(2)
June 2009
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