EP2SGX30CF780C4N Altera, EP2SGX30CF780C4N Datasheet - Page 127

IC STRATIX II GX 30K 780-FBGA

EP2SGX30CF780C4N

Manufacturer Part Number
EP2SGX30CF780C4N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX30CF780C4N

Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1927
EP2SGX30CF780C4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX30CF780C4N
Manufacturer:
ALTERA
0
Figure 2–82. Stratix II GX IOE in DDR Input I/O Configuration
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
DQS Local
2–82:
Bus (2)
sclr/spreset
clkin
ce_in
aclr/apreset
Chip-Wide Reset
Input Register
Input Register
D
CLRN/PRN
ENA
D
CLRN/PRN
ENA
Input RegisterDelay
I
nput Pin to
Q
Q
Note (1)
Stratix II GX Device Handbook, Volume 1
D
ENA
CLRN/PRN
To DQS Logic
Latch
Block (3)
Q
VCCIO
Stratix II GX Architecture
VCCIO
PCI Clamp (4)
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–119

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