EP2S15F672C3N Altera, EP2S15F672C3N Datasheet - Page 127

• Manufacturer Part Number: EP2S15F672C3N
• Description: IC STRATIX II FPGA 15K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S15F672C3N

• Number Of Logic Elements/cells: 15600
• Number Of Labs/clbs: 780
• Total Ram Bits: 419328
• Number Of I /o: 366
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Macrocells: 15600
• Family Type: Stratix II
• No. Of I/o's: 366
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 550MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1880; EP2S15F672C3N

Figure 3–2. Temperature vs. Temperature-Sensing Diode Voltage
Automated
Single Event
Upset (SEU)
Detection
Altera Corporation
May 2007
(Across Diode)
Voltage
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
–55
The temperature-sensing diode works for the entire operating range, as
shown in
The temperature sensing diode is a very sensitive circuit which can be
influenced by noise coupled from other traces on the board, and possibly
within the device package itself, depending on device usage. The
interfacing device registers temperature based on milivolts of difference
as seen at the TSD. Switching I/O near the TSD pins can affect the
temperature reading. Altera recommends you take temperature readings
during periods of no activity in the device (for example, standby mode
where no clocks are toggling in the device), such as when the nearby I/Os
are at a DC state, and disable clock networks in the device.
Stratix II devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. Some applications that require the device to
operate error free at high elevations or in close proximity to Earth’s North
or South Pole require periodic checks to ensure continued data integrity.
The error detection cyclic redundancy check (CRC) feature controlled by
–30
Figure
3–2.
–5
Temperature (˚C)
20
45
Stratix II Device Handbook, Volume 1
70
100 μA Bias Current
10 μA Bias Current
Configuration & Testing
95
120
3–13