EP2C50F672C8N Altera, EP2C50F672C8N Datasheet - Page 54

• Manufacturer Part Number: EP2C50F672C8N
• Description: IC CYCLONE II FPGA 50K 672-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C50F672C8N

• Number Of Logic Elements/cells: 50528
• Number Of Labs/clbs: 3158
• Total Ram Bits: 594432
• Number Of I /o: 450
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• No. Of Logic Blocks: 3158
• Family Type: Cyclone II
• No. Of I/o's: 450
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 320MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1690

I/O Structure & Features
Figure 2–24. Control Signal Selection per IOE
2–42
Cyclone II Device Handbook, Volume 1
Dedicated I/O
Clock [5..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
io_coe
io_csclr
io_caclr
io_cce_out
io_cce_in
io_cclk
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. You can
use the output register for data requiring fast clock-to-output
performance. The OE register is available for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, or the column and row interconnects. All
registers share sclr and aclr, but each register can individually disable
sclr and aclr.
configuration.
clk_in
Figure 2–25
clk_out
shows the IOE in bidirectional
ce_in
ce_out
aclr/preset
Altera Corporation
sclr/preset
February 2007
oe