EP1C12Q240C8 Altera, EP1C12Q240C8 Datasheet - Page 9
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EP1C12Q240C8
Manufacturer Part Number
EP1C12Q240C8
Description
IC CYCLONE FPGA 12K LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C12Q240C8
Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
173
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1081
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C12Q240C8
Manufacturer:
ALTERA
Quantity:
67
Company:
Part Number:
EP1C12Q240C8
Manufacturer:
XILINX
Quantity:
5
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EP1C12Q240C8
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
APTINA
Quantity:
3 000
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA
Quantity:
99
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA
Quantity:
348
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Altera Corporation
May 2008
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Figure 2–2
LAB
details the Cyclone LAB.
Local Interconnect
Row Interconnect
®
II Compiler places
Logic Array Blocks
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Preliminary
2–3