EP1C12Q240C8 Altera, EP1C12Q240C8 Datasheet - Page 21
![IC CYCLONE FPGA 12K LE 240-PQFP](/photos/6/72/67260/544-240-pqfp_sml.jpg)
EP1C12Q240C8
Manufacturer Part Number
EP1C12Q240C8
Description
IC CYCLONE FPGA 12K LE 240-PQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C12Q240C8
Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
173
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-MQFP, 240-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1081
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C12Q240C8
Manufacturer:
ALTERA
Quantity:
67
Company:
Part Number:
EP1C12Q240C8
Manufacturer:
XILINX
Quantity:
5
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EP1C12Q240C8
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
APTINA
Quantity:
3 000
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA
Quantity:
99
Company:
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA
Quantity:
348
Part Number:
EP1C12Q240C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
May 2008
Figure 2–10. LUT Chain and Register Chain Interconnects
The C4 interconnects span four LABs or M4K blocks up or down from a
source LAB. Every LAB has its own set of C4 interconnects to drive either
up or down.
LAB in a column. The C4 interconnects can drive and be driven by all
types of architecture blocks, including PLLs, M4K memory blocks, and
column and row IOEs. For LAB interconnection, a primary LAB or its
LAB neighbor can drive a given C4 interconnect. C4 interconnects can
drive each other to extend their range as well as drive row interconnects
for column-to-column connections.
Interconnect
Figure 2–11
Adjacent LE
Routing to
LUT Chain
Local
shows the C4 interconnect connections from a
Local Interconnect
Routing Among LEs
in the LAB
LE 10
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
Register Chain
Routing to Adjacent
LE's Register Input
MultiTrack Interconnect
Preliminary
2–15