EP3C120F780C8 Altera, EP3C120F780C8 Datasheet - Page 53

• Manufacturer Part Number: EP3C120F780C8
• Description: IC CYCLONE III FPGA 119K 780FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C120F780C8

• Number Of Logic Elements/cells: 119088
• Number Of Labs/clbs: 7443
• Total Ram Bits: 3981312
• Number Of I /o: 531
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2589 - KIT DEV EMB CYCLONE III EDITION544-2566 - KIT DEV DSP CYCLONE III EDITION544-2444 - KIT DEV CYCLONE III EP3C120544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-2391; 544-2531; 544-2531; EP3C120F780C8ES

Verification
Figure 13. Specifying the Number of Processors
© November 2008 Altera Corporation
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Preserving Performance
You can use the incremental compilation feature to preserve unchanged parts of your
design, thus preserving performance and allowing you to reach timing closure more
efficiently. For guidelines and references, refer to
Team-Based Design” on page
Reducing Compilation Time
You can speed up design iteration time by an average of 60% when making changes to
the design with the incremental compilation feature.
For guidelines and references, refer to the
Design” on page
The Quartus II software can run some algorithms in parallel to take advantage of
multiple processors and reduce compilation time when more than one processor is
available to compile the design. To set the number of processors available for a
Quartus II compilation, specify the Maximum processors allows for parallel
compilation on the Compilation Process Settings page of the Settings dialog box, as
in
parallel compilation.
Figure
13. The default value for the number of processors is 1, which disables
35.
35.
“Planning for Hierarchical and Team-Based
“Planning for Hierarchical and
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