EP1S10F780C7 Altera, EP1S10F780C7 Datasheet - Page 60
![IC STRATIX FPGA 10K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S10F780C7
Manufacturer Part Number
EP1S10F780C7
Description
IC STRATIX FPGA 10K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F780C7
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1112
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F780C7
Manufacturer:
EUTECH
Quantity:
3 930
Company:
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
Quantity:
44
Company:
Part Number:
EP1S10F780C7ES
Manufacturer:
ALTERA
Quantity:
89
Company:
Part Number:
EP1S10F780C7L
Manufacturer:
ALTERA
Quantity:
17
Company:
Part Number:
EP1S10F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S10F780C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
TriMatrix Memory
2–46
Stratix Device Handbook, Volume 1
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block’s data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers.
clock mode.
Figures 2–25
and
2–26
show the memory block in input/output
Altera Corporation
July 2005