EP2C15AF256I8N Altera, EP2C15AF256I8N Datasheet - Page 77
![IC CYCLONE II FPGA 15K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP2C15AF256I8N
Manufacturer Part Number
EP2C15AF256I8N
Description
IC CYCLONE II FPGA 15K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C15AF256I8N
Number Of Logic Elements/cells
14448
Number Of Labs/clbs
903
Total Ram Bits
239616
Number Of I /o
152
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
No. Of Macrocells
14448
Family Type
Cyclone II
No. Of I/o's
152
Clock Management
PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
320MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1780
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C15AF256I8N
Manufacturer:
ALTERA
Quantity:
586
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Altera Corporation
February 2007
Note to
(1)
CONFIG_IO
SignalTap II
instructions
Table 3–1. Cyclone II JTAG Instructions (Part 2 of 2)
JTAG Instruction
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
Table
3–1:
00 0000 1101
Instruction Code
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the USERCODE
register. In the Settings dialog box in the Assignments menu, click Device
& Pin Options, then General, and then turn on the Auto Usercode
option.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the
reset the configuration device.
device is reconfigured.
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
CONFIG_IO
Cyclone II Device Handbook, Volume 1
Description
nSTATUS
instruction holds
Configuration & Testing
is held low until the
nSTATUS
low to
3–3
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