EP1C12F256C8 Altera, EP1C12F256C8 Datasheet - Page 83
![IC CYCLONE FPGA 12K LE 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP1C12F256C8
Manufacturer Part Number
EP1C12F256C8
Description
IC CYCLONE FPGA 12K LE 256-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C12F256C8
Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
12060
# I/os (max)
185
Frequency (max)
275.03MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
12060
Ram Bits
239616
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1012
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C12F256C8
Manufacturer:
ALTERA
Quantity:
51
Company:
Part Number:
EP1C12F256C8
Manufacturer:
TI
Quantity:
7 000
Part Number:
EP1C12F256C8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1C12F256C8N
Manufacturer:
ALTERA
Quantity:
494
Company:
Part Number:
EP1C12F256C8N
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1C12F256C8N
Manufacturer:
ALTERA
Quantity:
20 000
Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
May 2008
unreg_data-out
reg_data-out
wraddress
rdaddress
rdclock
data-in
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
din
an
Figure 4–1
shown in
t
t
t
R4
C4
LOCAL
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
t
doutn-1
WEREH
doutn
Symbol
a0
b0
Table
shows the memory waveforms for the M4K timing parameters
t
t
DATACO1
WEREH
4–23.
t
DATACO2
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
a1
t
RC
doutn
dout0
a2
b1
t
t
WADDRSU
a3
WERESU
Parameter
dout0
din4
a4
b2
t
WADDRH
din5
a5
Timing Model
Preliminary
b3
din6
a6
4–13