EP1C12F256C8 Altera, EP1C12F256C8 Datasheet - Page 47

IC CYCLONE FPGA 12K LE 256-FBGA

EP1C12F256C8

Manufacturer Part Number
EP1C12F256C8
Description
IC CYCLONE FPGA 12K LE 256-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C12F256C8

Number Of Logic Elements/cells
12060
Number Of Labs/clbs
1206
Total Ram Bits
239616
Number Of I /o
185
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone®
Number Of Logic Blocks/elements
12060
# I/os (max)
185
Frequency (max)
275.03MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
12060
Ram Bits
239616
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1012

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0
Figure 2–28. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
May 2008
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one
comb_io_datain (combinatorial) input.
LAB Local
Interconnect
Figure
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
2–28:
LAB
io_datain[2..0] and
comb_io_datain[2..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5:0]
21
I/O Block
Row I/O Block
Contains up to
Row
Three IOEs
21 Data and
Control Signals
from Logic Array (1)
I/O Structure
Preliminary
2–41

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