EP1C6T144C8 Altera, EP1C6T144C8 Datasheet - Page 83

IC CYCLONE FPGA 5980 LE 144-TQFP

EP1C6T144C8

Manufacturer Part Number
EP1C6T144C8
Description
IC CYCLONE FPGA 5980 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C6T144C8

Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
98
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
98
Frequency (max)
275.03MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1058

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Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
Altera Corporation
May 2008
unreg_data-out
reg_data-out
wraddress
rdaddress
rdclock
data-in
wrclock
wren
rden
doutn-2
an-1
din-1
t
t
DATASU
WERESU
doutn-1
bn
t
DATAH
din
an
Figure 4–1
shown in
t
t
t
R4
C4
LOCAL
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
t
doutn-1
WEREH
doutn
Symbol
a0
b0
Table
shows the memory waveforms for the M4K timing parameters
t
t
DATACO1
WEREH
4–23.
t
DATACO2
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
a1
t
RC
doutn
dout0
a2
b1
t
t
WADDRSU
a3
WERESU
Parameter
dout0
din4
a4
b2
t
WADDRH
din5
a5
Timing Model
Preliminary
b3
din6
a6
4–13

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