ADSP-21375KSZ-2B Analog Devices Inc, ADSP-21375KSZ-2B Datasheet - Page 20

• Manufacturer Part Number: ADSP-21375KSZ-2B
• Description: IC DSP 32BIT 266MHZ 208-MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21375KSZ-2B

• Interface: DAI, DPI
• Clock Rate: 266MHz
• Non-volatile Memory: ROM (256 kB)
• On-chip Ram: 64kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21371/ADSP-21375
Power-Up Sequencing
The timing requirements for processor startup are given in
Table
Table 15. Power Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Based on CLKIN cycles.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
4097 cycles maximum.
15.
1
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
CLK_CFG1-0
RESETOUT
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
V
V
DDINT
RESET
CLKIN
DDEXT
DDINT
SRST
on Before V
specification in
t
RSTVDD
DDEXT
DDINT
DDINT
Table
/V
/V
DDEXT
DDEXT
17. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
Valid
Rev. B | Page 20 of 52 | June 2008
On
Figure 4. Power-Up Sequencing
t
IVDDEVDD
t
t
CLKVDD
PLLRST
t
CLKRST
Min
0
–50
0
10
20
4096
t
2
3
CORERST
t
CK
+ 2
t
CCLK
4, 5
Max
+200
200
Unit
ns
ms
ms
μs
μs