ADSP-2185BST-115 Analog Devices Inc, ADSP-2185BST-115 Datasheet - Page 12

• Manufacturer Part Number: ADSP-2185BST-115
• Description: IC DSP CONTROLLER 16BIT 100TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2185BST-115

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 28.8MHz
• Non-volatile Memory: External
• On-chip Ram: 80kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP

ADSP-2185
Target Board Connector for EZ-ICE
The EZ-ICE
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE
enough room in your system to fit the EZ-ICE
14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guidelines
listed below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device tim-
ing requirements and switching characteristics as specified in
this DSP’s data sheet. The performance of the EZ-ICE
approach published worst case specification for some memory
access timing requirements and switching characteristics.
Figure 7. Target Board Connector for EZ-ICE
®
* connector (a standard pin strip header) is shown
KEY (NO PIN)
0.1 inches. The pin strip header must have
ELOUT
RESET
GND
EBR
EBG
EE
13
11
1
3
5
9
7
TOP VIEW
12
14
10
®
4
2
6
8
®
* Probe
*. Be sure to allow
BG
EINT
BR
ELIN
ECLK
ERESET
EMS
®
* probe onto the
®*
®
may
*
®
*
®
*
–12–
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depend-
ing on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statisti-
cally vary in switching characteristic and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2185 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
system must have 10 k pull-up resistors connected when the
EZ-ICE
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE
at your option when the EZ-ICE
Target System Interface Signals
When the EZ-ICE
some system signals change. Design your system to be compat-
ible with the following system interface signal changes intro-
duced by the EZ-ICE
• EZ-ICE
• EZ-ICE
• EZ-ICE
• EZ-ICE
• EZ-ICE
between your target circuitry and the DSP on the RESET
signal.
between your target circuitry and the DSP on the BR signal.
stepping.
lator Space (DSP halted).
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE
®
®
* debugging sessions. These resistors may be removed
* is being used. The pull-up resistors are necessary
®
®
®
®
®
* emulation introduces an 8 ns propagation delay
* emulation introduces an 8 ns propagation delay
* emulation ignores RESET and BR when single-
* emulation ignores RESET and BR when in Emu-
* emulation ignores the state of target BR in certain
®
* board’s DSP.
®
* board is installed, the performance on
®
* board:
®
* is not being used.
REV. 0