ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 26

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ADSP-2173BST-80

Manufacturer Part Number
ADSP-2173BST-80
Description
IC DSP CONTROLLER 16BIT 128TQFP
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet

Specifications of ADSP-2173BST-80

Rohs Status
RoHS non-compliant
Interface
Host Interface, Serial Port
Clock Rate
20MHz
Non-volatile Memory
External
On-chip Ram
10kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Device Core Size
16b
Architecture
Enhanced Harvard
Format
Fixed Point
Clock Freq (max)
20MHz
Mips
20
Device Input Clock Speed
20MHz
Ram Size
10KB
Program Memory Size
24KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-2173BST-80
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
Parameter
Host Interface Port
Separate Data and Address (HMD1 = 0)
Read Strobe and Write Strobe (HMD0 = 1)
Timing Requirement:
t
t
t
t
t
Switching Characteristic:
t
t
t
t
t
t
NOTES
1
2
3
Start of Write or Read = HDS Low and HSEL Low.
End of Write or Read = HDS High and HSEL High.
Read or Write Pulse Width = HDS Low and HSEL Low.
HSU
HDSU
HWDH
HH
HRWP
HSHK
HKH
HDE
HDD
HRDH
HRDD
Host Write Cycle
Host Read Cycle
HA2–0, HRW Setup before Start of Write or Read
Data Setup before End of Write
Data Hold after End of Write
HA2–0, HRW Hold after End of Write or Read
Read or Write Pulse Width
HACK Low after Start of Write or Read
HACK Hold after End of Write or Read
Data Enabled after Start of Read
Data Valid after Start of Read
Data Hold after End of Read
Data Disabled after End of Read
HD15–0
HD15–0
HA2–0
HA2–0
HACK
HSEL
HACK
HRW
HDS
HSEL
HRW
HDS
Figure 15. Host Interface Port (HMD1 = 0, HMD0 = 1)
t
t
t
t
HSU
3
HDE
HDD
HSU
2
2
1
2
1
2
t
t
ADDRESS
HSHK
HSHK
ADDRESS
1
2
t
t
HRWP
HRWP
t
HDSU
–26–
2
DATA
DATA
1
t
t
HRDH
HRDD
t
t
HKH
t
HKH
t
HH
HH
Min
5
5
3
3
20
0
0
0
0
t
HWDH
Max
15
15
18
7
REV. A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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