ADSP-2173BST-80 Analog Devices Inc, ADSP-2173BST-80 Datasheet - Page 16

• Manufacturer Part Number: ADSP-2173BST-80
• Description: IC DSP CONTROLLER 16BIT 128TQFP
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2173BST-80

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Serial Port
• Clock Rate: 20MHz
• Non-volatile Memory: External
• On-chip Ram: 10kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Device Core Size: 16b
• Architecture: Enhanced Harvard
• Format: Fixed Point
• Clock Freq (max): 20MHz
• Mips: 20
• Device Input Clock Speed: 20MHz
• Ram Size: 10KB
• Program Memory Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-2171/ADSP-2172/ADSP-2173
Example Code
The following example is a code fragment that performs the
filter tap update for an adaptive (least-mean-squared algorithm)
filter. Notice that the computations in the instructions are
written like algebraic equations.
DO adapt UNTIL CE;
adapt:
Interrupt Enable
The ADSP-217x supports an interrupt enable instruction. Inter-
rupts are enabled by default at reset. The instruction source
code is specified as follows:
Syntax:
Description: Executing the ENA INTS instruction allows all
Interrupt Disable
The ADSP-217x supports an interrupt disable instruction. The
instruction source code is specified as follows:
Syntax:
Description: Reset enables interrupt servicing. Executing the
MF=MX0*MY1 (RND), MX0=DM (I2,M1); /* MF=error*beta */
MR=MX0*MF (RND), AY0=PM (I6,MS);
AR=MR1 + AY0, MX0=DM (I2,M1), AY0=PM (I6,M7);
PM(I6,M6) =AR, MR=MX0*MF (RND);
MODIFY (I2, M3);
MODIFY (I6, M7);
ENA INTS;
unmasked interrupts to be serviced again.
DIS INTS;
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
/* Point to oldest data */
/* Point to start of data */
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REV. A