ADSP-21060LCW-133 Analog Devices Inc, ADSP-21060LCW-133 Datasheet - Page 25

• Manufacturer Part Number: ADSP-21060LCW-133
• Description: IC DSP CONTROLLER 32BIT 240CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060LCW-133

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 33MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 240-CQFP Exposed Pad
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 33MHz
• Mips: 33
• Device Input Clock Speed: 33MHz
• Ram Size: 4MB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is the
Table 14. Memory Read—Bus Master
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
W = (number of wait states specified in WAIT register)
HI = t
H = t
Data delay/setup: user must meet t
The falling edge of MSx, SW, BMS is referenced.
Data hold: user must meet t
ACK delay/setup: user must meet t
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
SADADC
and dc loads.
CK
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
WR, DMAG
ADDRESS
MSx, SW
ADRCLK
BMS
Address Selects Delay to Data Valid
RD Low to Data Valid
Data Hold from Address, Selects
Data Hold from RD High
ACK Delay from Address, Selects
ACK Delay from RD Low
Address Selects Hold After RD High
Address Selects to RD Low
RD Pulse Width
RD High to WR, RD, DMAGx Low
Address, Selects Setup Before ADRCLK High
(OUT)
DATA
ACK
RD
HDA
or t
DAAK
DAD
HDRH
t
SADADC
or t
or t
or synchronous spec t
1
DRLD
DSAK
t
DARL
4
3
or synchronous specification t
or synchronous spec t
t
DAAK
2
3
2, 4
1, 2
t
HSDATI
DSAK
t
Figure 14. Memory Read—Bus Master
DAD
Rev. F | Page 25 of 64 | March 2008
. See
SSDATI
2
t
CK
Example System Hold Time Calculation on Page 47
t
DRLD
.
.
SACKC
for deassertion of ACK (low), all three specifications must be met for assertion of ACK (high).
t
RW
bus master accessing external memory space in asynchronous
access mode. Note that timing for ACK, DATA, RD, WR, and
DMAGx strobe timing parameters only applies to asynchronous
access mode.
Min
0.5
2.0
0+H
2 + 3DT/8
8 + 3DT/8 + HI
0 + DT/4
12.5 + 5DT/8 + W
5 V and 3.3 V
for the calculation of hold times given capacitive
t
HDRH
Max
18 + DT+W
12 + 5DT/8 + W
14 + 7DT/8 + W
8 + DT/2 + W
t
t
HDA
DRHA
t
RWR
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns