ADSP-21061LKS-160 Analog Devices Inc, ADSP-21061LKS-160 Datasheet - Page 6

• Manufacturer Part Number: ADSP-21061LKS-160
• Description: IC DSP CONTROLLER 1MBIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKS-160

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / RoHS Status: Not Compliant

ADSP-21061/ADSP-21061L
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
CLOCK
RESET
PRIORITY
BUS
011
010
001
3
3
3
CLKIN
RESET
RPBA
ID2–0
CLKIN
RESET
RPBA
ID2–0
CLKIN
RESET
RPBA
ID2–0
ADSP-21061 #2
ADSP-21061 #1
ADSP-21061 #6
ADSP-21061 #5
ADSP-21061 #4
ADSP-21061 #3
BR1–2, BR4–6
Figure 3. Shared Memory Multiprocessing System
BR1, BR3–6
ADDR31–0
ADDR31–0
DATA47–0
DATA47–0
ADDR31–0
CONTROL
CONTROL
DATA47–0
BR2–6
MS3–0
PAGE
REDY
SBTS
CPA
BR3
WRx
ACK
BMS
HBR
HBG
BR1
CPA
RDx
BR2
CS
Rev. C | Page 6 of 56 | July 2007
5
5
5
DMA transfers between external memory and external periph-
eral devices are another option. External bus packing to 16-, 32-
, or 48-bit words is performed during DMA transfers.
ADDR
ADDR
DATA
OE
WE
ACK
CS
CS
DATA
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
BOOT EPROM (OPTIONAL)
HOST PROCESSOR
INTERFACE (OPTIONAL)