ADSP-21061LKS-160 Analog Devices Inc, ADSP-21061LKS-160 Datasheet - Page 13

• Manufacturer Part Number: ADSP-21061LKS-160
• Description: IC DSP CONTROLLER 1MBIT 240MQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKS-160

• Rohs Status: RoHS non-compliant
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP, 240-PQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 128KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / RoHS Status: Not Compliant

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1 JTAG
test access port of the ADSP-2106x to monitor and control the
target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x’s CLKIN, TMS, TCK, TDI, TDO, and
GND signals be made accessible on the target system via a
14-pin connector (a 2-row, 7-pin strip header) such as that
shown in
connector for chip-on-board emulation. You must add this con-
nector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZ-
ICE connector and the farthest device sharing the EZ-ICE JTAG
pin should be limited to 15 inches maximum for guaranteed
operation. This length restriction must include EZ-ICE JTAG
signals that are routed to one or more ADSP-2106x devices, or a
combination of ADSP-2106x devices and other JTAG devices
on the chain.
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inches in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec. The BTMS, BTCK,
BTRST, and BTDI signals are provided so that the test access
port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure
board testing, tie BTRST to GND and tie or pull up BTCK to
V
up (through BTRST on the connector) or held low for proper
operation of the ADSP-2106x. None of the Bxxx pins (Pins 5, 7,
9, and 11) are connected on the EZ-ICE probe.
DD
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE Emulator
. The TRST pin must be asserted (pulsed low) after power-
5. If you are not going to use the test access port for
Figure
KEY (NO PIN)
5. The EZ-ICE probe plugs directly onto this
BTRST
BTMS
BTCK
GND
BTDI
GND
(Jumpers in Place)
11
13
1
3
5
7
9
TOP VIEW
9
14
10
12
2
4
6
8
EMU
GND
TMS
TCK
TRST
TDI
TDO
Rev. C | Page 13 of 56 | July 2007
The JTAG signals are terminated on the EZ-ICE probe as shown
in
Table 3. Core Instruction Rate/CLKIN Ratio Selection
1
Figure 6
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform oper-
ations such as starting, stopping, and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple
ADSP-21061 processors and the CLKIN pin on the EZ-ICE
header must be minimal. If the skew is too large, synchronous
operations may be off by one or more cycles between proces-
sors. For synchronous multiprocessor operation TCK, TMS,
CLKIN, and EMU should be treated as critical signals in terms
of skew, and should be laid out as short as possible on your
board. If TCK, TMS, and CLKIN are driving a large number of
ADSP-21061s (more than eight) in your system, then treat them
as a “clock tree” using multiple drivers to minimize skew. (See
Figure 7
tion” in the “High Frequency Design Considerations” section of
the ADSP-21061 SHARC User’s Manual, Revision 2.1.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU, and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
Signal
TMS
TCK
TRST
TDI
TDO
CLKIN
EMU
TRST is driven low until the EZ-ICE probe is turned on by the emulator at software
startup. After software startup, is driven high.
Table
1
3.
shows JTAG scan path connections for systems that
below and “JTAG Clock Tree” and “Clock Distribu-
Termination
Driven Through 22 Ω Resistor (16 mA Driver)
Driven at 10 MHz Through 22 Ω Resistor (16 mA
Driver)
Active Low Driven Through 22 Ω Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kΩ Resistor)
Driven by 22 Ω Resistor (16 mA Driver)
One TTL Load, Split Termination (160/220)
One TTL Load, Split Termination (160/220)
Active Low, 4.7 kΩ Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
ADSP-21061/ADSP-21061L