0W344-004-XTP ON Semiconductor, 0W344-004-XTP Datasheet - Page 20

• Manufacturer Part Number: 0W344-004-XTP
• Description: DSP BELASIGNA 200 AUDIO 52-NQFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 200r
• Type: Fixed Pointr

Specifications of 0W344-004-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 33MHz
• On-chip Ram: 42kB
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-TFQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -
• Voltage - I/o: -
• Voltage - Core: -

BelaSigna 200
7.1 Weighted Overlap-Add (WOLA) Filterbank Coprocessor
The WOLA coprocessor performs low-delay, high-fidelity filterbank processing to provide efficient time-frequency processing. The
coprocessor stores intermediate data values, program code and window coefficients in its own memory space. Audio data are
accessed directly from the input and output FIFOs where they are automatically managed by the IOP.
The WOLA coprocessor can be configured to handle different sizes and types of transforms, such as mono, simple stereo or full stereo
configurations. The number of bands, the stacking mode (even or odd), the oversampling factor, and the shape of the analysis and
synthesis windows used are all configurable. The selected set of parameters affects both the frequency resolution, the group delay
through the WOLA coprocessor and the number of cycles needed for complete execution.
The WOLA coprocessor can generate both real and complex data. Either real or complex gains can be applied. The RCore always has
access to these values through shared memories. All parameters are configurable with microcode, which is used to control the WOLA
during execution.
The RCore initiates all WOLA functions (analysis, gain applications, synthesis) through dedicated control registers. A dedicated
interrupt is used to signal completion of a WOLA function.
Many standard WOLA microcode configurations are delivered with the EDK. These configurations have been specially designed for low
group delay and high fidelity.
7.2 Input Output Processor (IOP)
The IOP is an audio-optimized configurable DMA unit for audio data samples. It manages the collection of data from the A/D converters
to the input FIFO and feeds digital data to the audio output stage from the output FIFO. The IOP can be configured to access data in
the FIFOs in four different ways:
• Mono mode: Input samples are stored sequentially in the input FIFO. Output samples are stored sequentially in the output FIFO.
• Simple stereo mode: Input samples from the two channels are stored interleaved in the input FIFO. Output samples for the single
• Digital mixed mode: Input samples from the two channels are stored in each half of the input FIFO. Output samples for the single
• Full stereo mode: Input samples from the two channels are stored interleaved in the input FIFO. Output samples for the two output
output channel are stored in the lower part of the output FIFO.
output channel are stored in the lower half of the output FIFO.
channels are stored interleaved in the output FIFO. (Note: A one-in, two-out configuration can be achieved in this mode by leaving
the second input unused).
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Figure 10: Four Audio Modes