0W344-004-XTP ON Semiconductor, 0W344-004-XTP Datasheet - Page 19

• Manufacturer Part Number: 0W344-004-XTP
• Description: DSP BELASIGNA 200 AUDIO 52-NQFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 200r
• Type: Fixed Pointr

Specifications of 0W344-004-XTP

• Interface: I²C, I²S, PCM, SPI, UART
• Clock Rate: 33MHz
• On-chip Ram: 42kB
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-TFQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Non-volatile Memory: -
• Voltage - I/o: -
• Voltage - Core: -

BelaSigna 200
Table 7: Instruction Set Continued
Table 8: Notation
Instruction
LDLC0/1 SIMM
LDSI A, SIMM
LDSI Rij, SIMM
MLD (Rj), (Ri) [,SQ]
MLD Reg, (Ri) [,SQ]
MODR Rj, Ri
MPYA (Rj), (Ri) [,SQ]
MPYA Reg, (Ri) [,SQ]
MPYS (Rj), (Ri) [,SQ]
MPYS Reg, (Ri) [,SQ]
MSET (Rj), (Ri) [,SQ]
MSET Reg, (Ri) [,SQ]
MUL [Cond] [,A] [,P]
NEG A [,Cond] [,DW]
NOP
OR A, Reg
OR A, (Rij)
OR A, DRAM [,B]
OR A, (Rij)p
OR A, Rc
ORI A, IMM
ORSI A, SIMM
POP Reg [,B]
POP Rc [,B]
PUSH Reg [,B]
PUSH Rc [,B]
Symbol
A
B
C
Cond
DRAM
DW
IE
IMM
Meaning
Accumulator update
Memory bank selection (X or Y)
Carry bit
Condition in status register
Low data (X or Y) memory address (8 bits)
Double word
Interrupt enable flag
Immediate data (16 bits)
OR memory with AH to AH
Description
Load loop counter with 8-bit unsigned
SIMM
Load A with signed SIMM
Load pointer register with unsigned
SIMM
Multiplier load and clear A
Multiplier load and clear A
Pointer register modification
Multiplier load and accumulate
Multiplier load and accumulate
Multiplier load and accumulate
negative
Multiplier load and accumulate
negative
Multiplier load
Multiplier load
Update A and/or PH | PL with X*Y on
condition
Calculate negative value of A on
condition
No operation
OR register with AH to AH
OR (DRAM) with AH to AH
OR program memory with AH to AH
OR Rc register with AH to AH
OR IMM with AH to AH
OR unsigned SIMM with AH to AH
Pop register from stack
Pop Rc register from stack
Push register on stack
Push Rc register on stack
Rev. 16 | Page 19 of 43 | www.onsemi.com
Symbol
INV
P
PRAM
Rc
Reg
Ri / Rj / Rij
SIMM
SQ
RET [B]
Instruction
PUSH IMM [,B]
REP n
REP Reg
REP (Rij)
RES Reg, Bit
RES (Rij), Bit
RND A
SET Reg, Bit
SET (Rij), Bit
SET_IE
SHFT n
SHFT A [,Cond] [,INV]
SLEEP [IE]
SUB A, Reg [,C]
SUB A, (Rij) [,C]
SUB A, DRAM [,B]
SUB A, (Rij)p [,C]
SUB A, Rc [,C]
SUBI A, IMM [,C]
SUSI A, SIMM
SWAP A [,Cond]
TGL Reg, Bit
TGL (Rij), Bit
TST Reg, Bit
TST (Rij), Bit
Meaning
Inverse shift
PH | PL update
Program memory address (16 bits)
Rc register (R0..7, PCFG0..2, PCFG4..6, LC0/1)
Data register (AL, AH, X, Y, ST, PC, PL, PH, EXT0, EXP, AE,
EXT3..EXT7)
Pointer to X / Y / either data memory
Short immediate data (10 bits)
Square
Description
Push IMM on stack
Repeat next instruction n+1 times
(9-bit unsigned)
Repeat next instruction Reg+1 times
Repeat next instruction (Rij)+1 times
Clear bit in register
Clear bit in memory
Return from subroutine
Round A with AL
Set bit in register
Set bit in memory
Set interrupt enable flag
Shift A by +/- n bits (6-bit signed)
Shift A by EXP bits on condition
Sleep
Subtract register from A
Subtract memory from A
Subtract (DRAM) from A
Subtract program memory from A
Subtract Rc register from A
Subtract IMM from A
Subtract signed SIMM from A
Swap AH, AL on condition
Toggle bit in register
Toggle bit in memory
Test bit in register
Test bit in memory